1. Technical Field
The present invention relates to a semiconductor chip housing tray used in a state being stacked in a plurality of stages. In particular, the invention relates to a semiconductor chip housing tray suppressing damage on a semiconductor chip when a plurality of the semiconductor chip housing trays are stacked.
2. Related Art
Chip on glass (COG) is one of methods for mounting a semiconductor chip. This method mounts a semiconductor chip having a bump directly on a substrate, and is becoming mainstream of a method for mounting a driver IC on a liquid crystal panel, for example. A semiconductor chip having a bump is housed in a manner allowing its active face on which the bump is formed to face upside when it is transferred so as to prevent the bump from being damaged. On the other hand, the active face needs to face downside when the semiconductor chip is mounted by COG. Therefore, the semiconductor chip housing tray needs to be turned over when the semiconductor chip is taken out from the tray.
FIGS. 7A and 7B are sectional views for explaining a first example of a semiconductor chip housing tray in related art. A semiconductor chip housing tray 210 shown in the figures is used in pairs with a tray 220 for taking out. An upper surface of the semiconductor chip housing tray 210 is divided into a plurality of semiconductor chip housing areas by a protruding part 211. An under surface of the tray 220 is divided into a plurality of semiconductor chip housing areas by a protruding part 221.
As shown in FIG. 7A, when semiconductor chips 201 are transferred, the semiconductor chips 201 are respectively housed in the plurality of semiconductor chip housing areas of the semiconductor chip housing tray 210. Then a plurality of the semiconductor chip housing trays 210 are stacked. When the semiconductor chips 201 are taken out, the tray 220 is stacked on the semiconductor chip housing tray 210 that is positioned topmost. The protruding part 221 contacts the protruding part 211 in this state.
As shown in FIG. 7B, the semiconductor chip housing tray 210 that is positioned topmost and on which the tray 220 is stacked is removed from a semiconductor chip housing tray 210 that is positioned one stage lower. Then the stacked body of the semiconductor chip housing tray 210 and the tray 220 is turned over. Accordingly, the semiconductor chips 201 are moved to the semiconductor chip housing areas of the tray 220. In the turning over of the stacked body, the semiconductor chips 201 are reversed, so that the active faces of the chips 201 face underside. This process is shown in FIGS. 7 and 8 in JP-A-10-211986, for example.
FIGS. 5A and 5B are sectional views for explaining a second example of a semiconductor chip housing tray in related art. In a semiconductor chip housing tray 230 shown in the figures, an upper surface is divided into a plurality of semiconductor chip housing areas by a protruding part 232 and an under surface is also divided into a plurality of semiconductor chip housing areas by a protruding part 231.
As shown in FIG. 8A, when semiconductor chips 201 are transferred, the semiconductor chips 201 are respectively housed in the plurality of semiconductor chip housing areas provided on the upper surface of the semiconductor chip housing tray 230. Then, a plurality of the semiconductor chip housing trays 230 are stacked up in a manner allowing their upper surfaces to face upside. The protruding part 231 contacts the protruding part 232 in this state. This process is shown in FIG. 2 of JP-A-10-211986, for example.
As shown in FIG. 8B, when the semiconductor chips 201 are taken out, a stacked body of the semiconductor chip housing trays 230 is turned over. Accordingly, the semiconductor chips 201 are moved to the semiconductor chip housing areas provided to the under surface of the semiconductor chip housing trays 230. In the turning over of the stacked body, the semiconductor chips 201 are reversed, so that the active faces of the chips 201 face downside. After that, the semiconductor chip housing trays 230 are removed one by one.
However, the semiconductor chip housing trays according to the first example and the second example have had the following problems. First, the semiconductor chip housing tray of the first example requires the tray for taking out. Further, the processes described in reference to FIGS. 7A and 7B are required for each of the trays, increasing the number of processes.
In the semiconductor chip housing tray according to the second example, a distance between the under surface of a semiconductor chip housing tray that is positioned one stage upper and the semiconductor chip tends to be large. Therefore, in a case where a planar shape of a semiconductor chip is rectangular and its short side is short, the semiconductor chips are turned over in the semiconductor chip housing areas, whereby the two surfaces are disadvantageously reversed.
Distortion and warpage sometimes occur in a semiconductor chip housing tray. In this case, in the semiconductor chip housing trays of the first example and the second example, a gap is produced between a semiconductor chip housing tray positioned upper and a semiconductor chip housing tray positioned lower, so that a semiconductor chip is caught in the gap, causing damage thereof.
For solving the problems described above, a height of the protruding part on the upper surface and that on the under surface of the semiconductor chip housing tray according to the second example may be formed to be nearly half of the thickness of the semiconductor chips. However, this case impairs the settlement of the semiconductor chips in the semiconductor chip housing areas, so that the semiconductor chips pop out from the semiconductor chip housing areas due to some vibration or shock, damaging the semiconductor chips.
To the above problems, JP-A-2007-109763 discloses following semiconductor chip housing tray. When a plurality of the semiconductor chip hosing trays are stacked, a rib partially provided to an under surface of one semiconductor chip housing tray along boundaries of its housing areas engages with a rib partially provided to an upper surface of another semiconductor chip housing tray that is positioned one stage lower along boundaries of its housing areas. Accordingly, a distance between the under surface of the semiconductor chip housing tray that is positioned one stage upper and the semiconductor chip can be made short, and the semiconductor chips can be prevented from popping out from the housing areas.
In the semiconductor chip housing tray disclosed in JP-A-2007-109763, the rib partially provided to the under surface of the semiconductor chip housing tray along boundaries of its housing areas engages with the rib partially provided to the upper surface of the semiconductor chip housing tray that is positioned one stage lower along boundaries of its housing areas. Therefore, when the plurality of semiconductor chip housing trays are stacked, the rib provided on the under surface may damage the semiconductor chips housed in the semiconductor chip housing tray that is positioned one stage lower.